/**********************************************************************************************************************
 *  COPYRIGHT
 *  -------------------------------------------------------------------------------------------------------------------
 *
 *                This software is copyright protected and proprietary to Vector Informatik GmbH.
 *                Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
 *                All other rights remain with Vector Informatik GmbH.
 *  -------------------------------------------------------------------------------------------------------------------
 *  FILE DESCRIPTION
 *  -------------------------------------------------------------------------------------------------------------------
 *          File:  Rte_CtCdA2b.h
 *        Config:  S32K144_Start.dpa
 *   ECU-Project:  AMP
 *
 *     Generator:  MICROSAR RTE Generator Version 4.19.0
 *                 RTE Core Version 1.19.0
 *       License:  CBD1800257
 *
 *   Description:  Application header file for SW-C <CtCdA2b>
 *********************************************************************************************************************/

/* double include prevention */
#ifndef _RTE_CTCDA2B_H
# define _RTE_CTCDA2B_H

# ifndef RTE_CORE
#  ifdef RTE_APPLICATION_HEADER_FILE
#   error Multiple application header files included.
#  endif
#  define RTE_APPLICATION_HEADER_FILE
#  ifndef RTE_PTR2ARRAYBASETYPE_PASSING
#   define RTE_PTR2ARRAYBASETYPE_PASSING
#  endif
# endif

# ifdef __cplusplus
extern "C"
{
# endif /* __cplusplus */

/* include files */

# include "Rte_CtCdA2b_Type.h"
# include "Rte_DataHandleType.h"


# define CtCdA2b_START_SEC_CODE
# include "CtCdA2b_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */

/**********************************************************************************************************************
 * Runnable entities
 *********************************************************************************************************************/

# ifndef RTE_CORE
#  define RTE_RUNNABLE_RCtCdA2b_Init A2b_Init
#  define RTE_RUNNABLE_RCtCdA2b_Mainfunction A2b_Mainfunction
#  define RTE_RUNNABLE_RCtCdA2b_ReadRemotePeri A2b_ReadRemotePeri
#  define RTE_RUNNABLE_RCtCdA2b_ReadRemotePin A2b_ReadRemotePin
#  define RTE_RUNNABLE_RCtCdA2b_WriteRemotePeri A2b_WriteRemotePeri
#  define RTE_RUNNABLE_RCtCdA2b_WriteRemotePin A2b_WriteRemotePin
#  define RTE_RUNNABLE_RCtcdA2b_NetworkSetup A2b_NetworkSetup
# endif

FUNC(void, CtCdA2b_CODE) A2b_Init(void); /* PRQA S 0850, 3451 */ /* MD_MSR_19.8, MD_Rte_3451 */
FUNC(void, CtCdA2b_CODE) A2b_Mainfunction(void); /* PRQA S 0850, 3451 */ /* MD_MSR_19.8, MD_Rte_3451 */
FUNC(Std_ReturnType, CtCdA2b_CODE) A2b_ReadRemotePeri(uint16 NetworkId, uint8 NodeAddr, uint8 ChipAddr, uint8 RegAddr, uint8 Length, pUint8 Buf); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, CtCdA2b_CODE) A2b_ReadRemotePin(uint16 NetworkId, uint8 NodeAddr, uint8 Pin, pUint8 Val); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, CtCdA2b_CODE) A2b_WriteRemotePeri(uint16 NetworkId, uint8 NodeAddr, uint8 ChipAddr, uint8 RegAddr, uint8 length, pUint8 buf); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, CtCdA2b_CODE) A2b_WriteRemotePin(uint16 NetworkId, uint8 NodeAddr, uint8 Pin, boolean Val); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, CtCdA2b_CODE) A2b_NetworkSetup(uint16 NetworkId); /* PRQA S 0850 */ /* MD_MSR_19.8 */

# define CtCdA2b_STOP_SEC_CODE
# include "CtCdA2b_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */


# ifndef RTE_CORE
/**********************************************************************************************************************
 * Application errors
 *********************************************************************************************************************/

#  define RTE_E_PiA2bIf_E_A2B_READ_FAILED (3U)

#  define RTE_E_PiA2bIf_E_A2B_SETUP_FAILED (1U)

#  define RTE_E_PiA2bIf_E_A2B_WRITE_FAILED (2U)
# endif /* !defined(RTE_CORE) */

# ifdef __cplusplus
} /* extern "C" */
# endif /* __cplusplus */

#endif /* _RTE_CTCDA2B_H */

/**********************************************************************************************************************
 MISRA 2004 violations and justifications
 *********************************************************************************************************************/

/* module specific MISRA deviations:
   MD_Rte_3451:  MISRA rule: 8.8
     Reason:     Schedulable entities are declared by the RTE and also by the BSW modules.
     Risk:       No functional risk.
     Prevention: Not required.

*/
